Some applications, such as hard disk read channels or wideband wireless standards, require a low-resolution (for example, approximately 6 bit), high-speed (for example, greater than 1 Giga-samples per second (GS/s)) analog-to-digital converter (ADC).
Traditionally there are two architectures for low-resolution high-speed ADCs: time-interleaved Successive Approximation Register (SAR) converters and flash converters. Single-channel SAR converters typically operate at sampling frequencies of a few hundred megasamples per second (MS/s) (for example, approximately 300 MS/s). As a result, a large number of channels would need to be interleaved, yielding a large input capacitance. Depending on the chosen approach, a time-interleaved SAR architecture for the same specifications could have an input capacitance 10-20 times larger than a pipelined binary search ADC. Flash converters on the other hand would be severely limited by quantized power, as for each conversion 63 comparisons (6 bit) would have to be made at low noise/offset. The power requirement for similar specifications with a calibrated flash converter would be 10 times larger than the power consumption in a pipelined binary search ADC.
Pipelined analog-to-digital converters have become popular for sampling rates from a few megasamples per second up to 100 megasamples per second. Dynamic pipelined conversion enables low power quantization at high speed with low input capacitance but requires calibration.
US patent application US2005/0062635 introduces a pipelined analog-to-digital converter that follows a non-linear scale and allows operation at frequencies of 2 GHz and more. The pipelined ADC comprises a number of comparator stages where the thresholds of the comparator stages are adjusted in accordance with the digital conversion results from the previous stage. To summarize, an architecture and method are proposed in this document to provide a pipelined ADC with a programmable characteristic so even a non-linear scale may be implemented. The output signals are processed via linear signal processing, using linear amplifiers.